The present disclosure relates generally to electrostatic device protection for semiconductor devices.
Electrostatic discharge, hereinafter “ESD,” is a common phenomenon that occurs during handling of semiconductor integrated circuit (“IC”) devices. An electrostatic charge may accumulate for various reasons and produce potentially destructive effects on an IC device. Damage typically may occur during a testing phase of IC fabrication or during assembly of the IC onto a circuit board, as well as during use of equipment into which the IC has bean installed. Damage to a single IC due to poor ESD protection in an electronic device can partially or sometimes completely hamper its functionality. ESD protection for semiconductor ICs is, therefore, a reliability issue of paramount concern.
Typically, there are few gate-coupled effects between an I/O pad and a first poly gate, if any at all. A prior art dynamic floating gate circuit 1 is shown in FIG. 1. A Resistor-Capacitor (RC) circuit 3 is electrically located between a voltage bus 5 and a ground or ground voltage 4. The I/O pad 2 is connected to an I/O bus 6. The floating gate circuit 1 is constrained in that the PMOS side 7 must have diode path shown as 10 to charge the RC circuit 3 for controlling the floating gate of the cascaded transistors. Because of this constraint dynamic floating gate circuits, while acceptable for regular (non-HVT) I/O applications, are not useful in HVT applications.
FIG. 2 is a prior art ESD circuit 200 for HVT I/O applications. The circuit 200 contains two sets of cascaded NMOS transistors 230 and 240. The first poly gate in each set is typically tied to the voltage bus 5, e.g. a 3.3 v bus. Similar to many prior art circuits, the circuit 200 includes a soft pull component 203, e.g. a dynamic floating gate similar to that shown in FIG. 1. The soft pull component 203, however, may not function due to PMOS floating well blocking in the diode path from the input/output (I/O) pad 2 to the voltage bus 5. As a result, there is no gate-coupling effect and the fingers, whether used or not used, may be non-uniformly triggered by an ESD event, e.g. path 210 and path 211 are not uniform. This results in a poor level of ESD protection and necessitates an ESD implant. Unfortunately, the ESD implant requires changes to the mask and, hence, increases costs and complexity. Additionally it would be advantageous for a circuit level ESD protection scheme independent of the mask for the IC which would also reduce cell size. Such a circuit level ESD protection would beneficially be available for use with existing ICs.
Therefore, in order to obviate the deficiencies in the prior art, it is an object of the present disclosure to present an ESD protection circuit for HVT I/O devices. The circuit in one embodiment having a first circuit coupled to a voltage bus and to the gate of a first transistor, the first circuit comprising a metal-oxide semiconductor (MOS) transistor (11); and a second circuit coupled to the ground and to the gate of the transistor (11) of the first circuit.
It is also an object of the present disclosure to present an improved circuit for providing high voltage tolerant ESD protection for a semiconductor circuit. The improvement including a gate coupling circuit between the first transistors of each of two cascaded transistor sets.
It is another object of the present disclosure to present in a circuit for providing high voltage tolerant ESD protection for a semiconductor, a method for improving ESD protection. The method including providing a gate coupling circuit between the first transistors of two cascaded transistor sets; removing one or more of the plurality of fingers; removing the soft pull circuit; and, tying-off one or more of the cascaded transistor sets.
It is still another object of the present disclosure to present in a circuit for providing high voltage tolerant ESD protection for a semiconductor circuit a method for uniformly turning on each of the fingers during an ESD event. The method including coupling the gates of the first transistors of the cascaded transistor sets with a gate coupling circuit.
These objects and other advantages of the disclosed subject matter will be readily apparent to one skilled in the art to which the disclosure pertains from a perusal or the claims, the appended drawings, and the following detailed description of the preferred embodiments